A New Approach for Multiprocessor System-On-Chip Application Scheduling in Multi-Objective Flow Shops

The flow shop scheduling problem in Multiprocessor-System-on-Chip (MPSoC) architectures presents challenges for traditional optimization algorithms, especially when addressing multiple conflicting objectives. Hence, advanced optimization approaches are required to tackle these objectives simultaneously. Therefore, this research aims to propose and evaluate a new optimization approach based on the integration of the Fire Hawk Optimizer with the Smart Battery Scheduling Algorithm (FHO-SBSA) to address the multi-objective (make span, CPU time, global average delay, network throughput, and total energy consumption) flow shop scheduling problem in MPSoC systems. To evaluate the performance of the FHO-SBSA optimization approach, two benchmark applications were selected, with ten instances assessed. The FHO-SBSA was compared against Practical Swarm Optimization (PSO) and Genetic Algorithm (GA) in solving the MOFSS problem. Additionally, the optimization effectiveness of FHO-SBSA was evaluated at two distinct levels: computational efficiency at the MPSoC IP core level and communication efficiency with the Network-on-Chip (NoC) architecture. The comparative analysis included performance metrics both before and after fine-tuning the algorithm, with a specific focus on area occupancy. The evaluation was conducted across multiple mesh grid sizes to assess the impact of the optimization on system performance comprehensively. Results: Experimental results show that FHO-SBSA outperforms GA and PSO in all measured aspects. It achieved makespan values ranging from 971.0 to 1332.0 and maintained low CPU time between 0.0315s and 0.0807s. In comparison, GA and PSO yielded higher makespan values and required longer processing times. Additionally, FHO-SBSA demonstrated improved energy consumption and communication efficiency. Implications: By applying FHO-SBSA, MOFSS can be optimally solved in NoC-based MPSoC systems, where performance is parallel to power consumption. Significant for high-performance energy-critical real-time applications in next-generation MPSoC design, enhancing system performance in computationally challenging tasks.