A Novel Offset Compensation Technique for a High Speed Flash ADC

In this paper, an 8 bit 500 MSPS Flash ADC has been presented which incorporates a ramp signal based offset compensation technique. The comparator used in the flash ADC is of Threshold-Inverter-Quantization (TIQ) concept. For TIQ-based comparators, the offset voltage is a function of the individual threshold voltages of the NMOS and PMOS transistors, voltage supply variation and aspect ratios of the transistors. In this work, a 180-nm CMOS process technology has been used to implement the comparator circuits. Monte-Carlo analysis of the TIQ-based comparators show a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3-\sigma$</tex> variation of 6.79 mV, which equates to a value of 3 LSB for the ADC, having a dynamic range of 500 mV. In order to compensate the offset voltage, a ramp signal is used at a sampling speed of 10 MHz. Cumulative values of the thermometric codes thus generated are compared with ideal values to perform the compensation procedure. With <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 3$</tex> LSB random offset of all the comparators, the ADC provides an ENOB of 5.139 bits. Post compensation, the ENOB improves to 7.73 bits.