On the Design of CMOS Ring Oscillators Using Geometric Programming

Ring oscillators are widely used for on-chip systems due to their low area usage. This work presents a method for the design of CMOS ring oscillators using Geometric Programming (GP) together with a compact MOSFET model specially adapted for GP. A formulation for the design of ring oscillators is presented, where all design variables, expressions, and constraints are shown and explained. A case study is defined for a 1-GHz ring oscillator in a 65nm technology. The problem is then solved using the CVX package for Octave and final results are evaluated using simulations with BSIM4 models in the Ngspice electrical simulator. Comparison between the optimized values (assessed by design equations) and simulations resulted in an error of $\mathbf{2 . 2 \%}$ for frequency and $\mathbf{1 . 8 \%}$ for power. The results achieved the design goals, with a 1.022 GHz frequency, $39 \mu \mathrm{~W}$ (the smallest among compared works), and a phase noise at 100 MHz of -132.6 dBc/Hz.