SCOoOTER: A RISC-V Processor Framework and Tool Flow for an Architecture-to-Layout Design Course

This paper introduces SCOoOTER, an open-source, highly-configurable RISC-V processor designed for courses on advanced processor architecture and design, reaching from architecture down to chip implementation. SCOoOTER offers students the opportunity to explore and extend processor functionality through a modular architecture and a wide range of configuration options, incorporating advanced architectural concepts such as dynamic instruction scheduling, speculative execution, branch prediction, and multithreading, providing a rich environment for hands-on learning. The processor is integrated with several educational tools, such as automated testing suites, debugging tools, built-in performance evaluation, and FPGA and ASIC design generation, enabling students to efficiently explore and validate different design decisions down to the physical layer. Except for FPGA synthesis and (optional) functional verification, SCOoOTER exclusively relies on freely available, open-source tools to ensure accessibility and avoid cumbersome NDAs, high per-seat EDA licensing costs, and the associated organizational overhead. Our evaluation shows that SCOoOTER achieves competitive performance to the CVA6 application-class processor, while also being more accessible to novice users due to its education-focused documentation and extensive integration and evaluation tools. Furthermore, SCOoOTER is aligned with widely-used textbooks on processor design, making it an ideal platform for students to learn and apply modern processor architecture concepts. Additionally, we highlight the potential for students to enhance SCOoOTER by implementing additional functionalities, which serves as a hands-on introduction to modern processor design and optimization techniques. Overall, SCOoOTER serves as a powerful educational platform that enables students to engage deeply with processor architecture at all abstraction levels and gain experience relevant to both research and industry practices in processor design.