CohereSim: An Extensible Simulator for Cache Coherence and the Experiments that it Supports

Cache coherence is a core topic in a parallel computer architecture course. The choice of protocol and other cache design parameters influences the performance of software that shares data across processors, so an in-depth understanding of them is a must-have. This paper discusses an L1 cache simulator that can simulate both SMP and DSM protocols. Students are given the skeleton of a simulator and an implementation of one or more protocols. They are asked to construct implementations of additional protocols, and then measure their performance on traces from standard benchmark suties. The simulator also offers an interactive mode that reports performance metrics after each individual memory access as the student enters them. This simulator is built in C++ and designed with modularity and extensibility in mind, enabling and encouraging further development to add support for more protocols. The paper describes the structure of the simulator, the coherence protocols that have been implemented, as well as sample assignments.