Dynamic pass bias control for temperature-resilient neural networks using vertical NAND flash memory
Vertical NAND (V-NAND) flash memory has emerged as a promising candidate for neuromorphic computing platforms due to its high density, scalability, and reliability. However, synaptic weights stored in V-NAND cells are highly sensitive to ambient temperature variations, resulting in significant conductance shifts that degrade the inference accuracy of neural networks. To address this challenge, we propose a dynamic pass bias (DPB) control scheme that compensates for temperature-induced weight variations without requiring memory reprogramming or additional hardware overhead. By adaptively adjusting the pass bias applied to unselected word-lines during read operations, the DPB scheme effectively stabilizes the differential conductance representation of weights under thermal fluctuations. In addition, we introduce a temperature-adaptive biasing circuit composed of a single-crystalline silicon MOSFET and V-NAND strings. Exploiting their opposing temperature-dependent resistance characteristics, this passive circuit naturally reduces the pass bias as temperature rises, enabling real-time analog compensation without explicit sensing or digital control logic. Experimental measurements on commercial V-NAND devices fabricated with over 100 WL layers reveal substantial shifts in bit-line currents with increasing temperature. Simulation results based on CIFAR-10 image classification using a VGG-11 network demonstrate that the DPB scheme significantly mitigates accuracy degradation across a wide temperature range. Notably, adjusting pass bias at lower temperatures improves classification accuracy by up to 10.5%p compared to conventional fixed-bias operations. These results highlight the effectiveness of dynamic pass bias control-both digitally and circuit-assisted-as a lightweight and scalable solution for enhancing the temperature resilience of V-NAND flash memory-based neural networks.
Authors
- Joon Hwang (ORCID: https://orcid.org/0000-0003-2998-8174)
- Yeongheon Yang (ORCID: https://orcid.org/0009-0004-3117-0528)
- Ryun‐Han Koo (ORCID: https://orcid.org/0000-0002-5708-3308)
- Jonghyun Ko (ORCID: https://orcid.org/0000-0001-5641-2352)
- Jiseong Im (ORCID: https://orcid.org/0000-0002-7260-9224)
- In-Seok Lee
- Mi‐Hwa Oh (ORCID: https://orcid.org/0000-0001-7838-5260)
- Jong-Won Back
- Gyuweon Jung (ORCID: https://orcid.org/0000-0003-0357-0933)
- Donghyun Shin (ORCID: https://orcid.org/0000-0002-0819-0553)
- Sungho Park (ORCID: https://orcid.org/0000-0001-7416-1059)
- Jong‐Ho Lee (ORCID: https://orcid.org/0000-0003-3559-9802)
Institutions
- SK Group (United States) (US)
- Seoul National University (KR)
- National University College (PR)
Publication Details
- Journal
- Nano Convergence
- Published
- 2025-09-30
- DOI
- https://doi.org/10.1186/s40580-025-00513-1
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- SK Hynix
- National Research Foundation
- Seoul National University
- National Research Foundation of Korea
- Ministry of Science and ICT, South Korea