Reinforcement Guided Genetic Algorithm for Application Mapping in Network-on-Chip Architectures: Toward Transparent and Efficient MPSoC Scheduling

In this paper, we present a novel hybrid application mapping framework that integrates Genetic Algorithm (GA) with Reinforcement Learning (RL) to optimize task allocation in 2D Network-on-Chip based Multiprocessor System-on-Chip (NoC-based MPSoC) architectures. The goal is to reduce overall communication costs and improve runtime efficiency during the task-to-core mapping process. The RL agent is embedded within the GA loop to dynamically steer selection, crossover, and mutation operations using real-time feedback on mapping quality. Our methodology is evaluated on both real applications (e.g., PIP, MPEG, VOPD) and synthetic TGFF workloads across NoC mesh sizes from 3x3 to 12x11. Experimental results demonstrate that GA+RL consistently outperforms the baseline GA. For instance, in the TGFF-G5 benchmark (80 cores), the GA+RL approach achieved a minimum communication cost of 116.354, compared to 244.645 with original GA, representing over 52% improvement. Across all trials, GA+RL also showed lower standard deviations and earlier convergence generations. To improve interpretability, we incorporate Explainable AI (XAI) techniques using SHapley Additive exPlanations (SHAP) to analyze feature contributions. Results reveal that average communication hops and total bandwidth are key factors influencing mapping efficiency. The GA+RL model demonstrates greater transparency and consistency, aiding design-time decisions. This work has direct implications for industrial platforms, including Kalray MPPA-256 (autonomous vehicles), Intel SCC (cloud/HPC), Adapteva Epiphany (IoT Edges), and Tilera TILE-Gx (Cybersecurity), where efficient and adaptive application mapping is critical. Aligned with UN SDG 2 (Zero Hunger), the framework also supports real-time scheduling in agriculture IoT systems, enabling energy-efficient deployment of smart technologies to enhance food production and sustainability.

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Publication Details

Journal
IEEE Access
Published
2025-01-01
DOI
https://doi.org/10.1109/access.2025.3616179
Citations
1
Primary Topic
Interconnection Networks and Systems
Type
article
Field-Weighted Citation Impact
1.49
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article

Reinforcement Guided Genetic Algorithm for Application Mapping in Network-on-Chip Architectures: Toward Transparent and Efficient MPSoC Scheduling

Walid El‐Shafai, Ahmad Taher Azar, Ahmed Abbas Jasim Al-Hchaimi, ‪Mahmood A. Al-Shareeda‬‏
1 citations
IEEE Access
Interconnection Networks and Systems
1.49
article

Reinforcement Guided Genetic Algorithm for Application Mapping in Network-on-Chip Architectures: Toward Transparent and Efficient MPSoC Scheduling

Walid El‐Shafai, Ahmad Taher Azar, Ahmed Abbas Jasim Al-Hchaimi, ‪Mahmood A. Al-Shareeda‬‏
article en
1 citations

Abstract

In this paper, we present a novel hybrid application mapping framework that integrates Genetic Algorithm (GA) with Reinforcement Learning (RL) to optimize task allocation in 2D Network-on-Chip based Multiprocessor System-on-Chip (NoC-based MPSoC) architectures. The goal is to reduce overall communication costs and improve runtime efficiency during the task-to-core mapping process. The RL agent is embedded within the GA loop to dynamically steer selection, crossover, and mutation operations using real-time feedback on mapping quality. Our methodology is evaluated on both real applications (e.g., PIP, MPEG, VOPD) and synthetic TGFF workloads across NoC mesh sizes from 3x3 to 12x11. Experimental results demonstrate that GA+RL consistently outperforms the baseline GA. For instance, in the TGFF-G5 benchmark (80 cores), the GA+RL approach achieved a minimum communication cost of 116.354, compared to 244.645 with original GA, representing over 52% improvement. Across all trials, GA+RL also showed lower standard deviations and earlier convergence generations. To improve interpretability, we incorporate Explainable AI (XAI) techniques using SHapley Additive exPlanations (SHAP) to analyze feature contributions. Results reveal that average communication hops and total bandwidth are key factors influencing mapping efficiency. The GA+RL model demonstrates greater transparency and consistency, aiding design-time decisions. This work has direct implications for industrial platforms, including Kalray MPPA-256 (autonomous vehicles), Intel SCC (cloud/HPC), Adapteva Epiphany (IoT Edges), and Tilera TILE-Gx (Cybersecurity), where efficient and adaptive application mapping is critical. Aligned with UN SDG 2 (Zero Hunger), the framework also supports real-time scheduling in agriculture IoT systems, enabling energy-efficient deployment of smart technologies to enhance food production and sustainability.

IEEE AccessVol. 13
Prince Sultan University (SA), Southern Technical University (IQ)
Openalex Percentile: Top 13%
Interconnection Networks and Systems
1.49
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