A Lightweight CBDNet Hardware Accelerator for Image Denoising

With the widespread application of deep learning in image denoising, the high computational complexity of convolutional neural networks has become a major bottleneck for inference on edge devices. This study proposes a lightweight convolutional blind denoising network and its efficient hardware accelerator implementation, achieved through algorithmic optimizations that reduce computational complexity and hardware-level enhancements that improve inference efficiency. A $64 \%$ reduction in parameters compared to the original network enables efficient deployment on edge devices with constrained compute and memory. A reconfigurable hybrid-dataflow systolic array is employed to dynamically configure compute units and data paths for different convolution types with varying parallelism. The model has been validated through FPGA prototyping, with the accelerator achieving a computational efficiency of 0.084 GOPS/PE on image denoising tasks, providing a viable hardware solution for edge computing scenarios.