Parallel Acceleration and Pipeline Optimization: Accelerator Design for Edge Devices Based on YOLOv4-tiny

With the widespread adoption of edge computing in fields such as autonomous driving, the Internet of Things (IoT) and intelligent surveillance, the demand for real-time performance and low power consumption has become increasingly critical. However, existing FPGA-based neural network accelerators still face significant performance and power bottlenecks when processing lightweight object detection models, making them difficult to deploy on resource-constrained edge devices. To address this issue, this paper proposes a neural network accelerator designed to accelerate the YOLOv4-tiny model. The accelerator features a multi-dimensional parallel computing architecture and efficient data flow optimization. Through a four-dimensional parallel strategy and a dual-buffer interleaved access mechanism, it significantly enhances computational efficiency and the utilization of computing units, overcoming the limitations of traditional FPGA solutions to achieve high performance and low power consumption in edge AI inference. The proposed accelerator achieves a peak performance of 68.4 GOPS at a clock frequency of 150 MHz. Compared to similar FPGA-based solutions, it improves energy efficiency by $2.5 \times$ to $4.92 \times$, achieves a $31.6 \%$ increase in energy efficiency, and a $52.3 \%$ boost in performance, while maintaining a low power consumption of just 4.294 W. The design utilizes only 29,739 LUTs, 94 BRAMs and 228 DSPs. With its powerful computational capabilities, the accelerator is well-suited for edge applications and embedded systems, offering a practical solution for FPGA-based AI inference acceleration.