Optimization of Flip-Chip Reflow Soldering Process and Thermal Stress Study of 2D Digital SiP with High-Density BGA Chip

We developed a two-dimensional (2D) digital chip system in a package (SiP) consisting of a large-sized programmable logic array (FPGA) chip with tens of thousands of solder bumps and three small-sized silicon-based ball grid array (BGA) chips flip-chip soldered onto a composite organic substrate. The electrical connections of SiP were monitored by the daisy chain circuits designed between the chip and substrate. By improving the reflow temperature curve of the flip chip bonding, the high-density bump flip soldering process of this 2D digital chip SiP was optimized. The daisy chain resistance test results showed that the SiP achieved full electrical connections at all testing ports. The analysis of CT scan analysis and X-ray inspection indicated that the solder joints had no offset and normal morphology. The warpage and thermal stress distribution of the SiP after reflow were analyzed through thermal deformation testing, measuring microscope, and ANSYS thermal stress simulation. The results would be beneficial for the soldering process and the stability improvement of the solder joint for these digital SiP with high-density BGA chip.