Memguard-RW: Improved Real-Time Memory Bandwidth Regulation Within a Hypervisor

Memory bandwidth is a critical factor in the performance of DRAM-based computing architectures, particularly in memory-intensive computations. Modern multi-core processors share critical resources, such as main memory and cache, which impact the predictability of real-time systems due to resource contention. Techniques like memory access regulation, cache partitioning, and static hypervisors aim to mitigate this contention. This paper presents an improvement of a memory control mechanism based on MemGuard, named MemGuard-RW, designed and implemented within a hypervisor. MemGuard-RW uses two performance counters for measuring the memory accesses, one for memory readings and another one for writings, thus decreasing the pessimism on the original memory access budget from MemGuard. Additionally, we extend the MemGuard schedulability analysis considering the two-counter approach. To evaluate the effectiveness of the implementation and analysis, we deployed FreeRTOS as a guest alongside three stress-generating guests, measuring the interference experienced by the FreeRTOS instance and comparing the analysis with two counters with the original analysis with one counter, using modern benchmarks. The results demonstrate that the proposed mechanism successfully regulates memory accesses, showing its potential for enhancing the predictability and performance of real-time systems in multi-core environments. Our proposed analysis with two counters reduces the upper bound of around 20 % for tasks having medium and high memory usage.