A 12-Bit 50MHz SAR-ADC with an On-chip Sampling Signal Generator Module

We here demonstrate a noble architecture of a 12-bit SAR-ADC featuring a tail capacitor dynamic comparator and an automatic on-chip sampling signal generator. By eliminating the conventional bootstrap switches, this design effectively reduces the core chip area to 0.88 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The sampling signals of the proposed ADC are created by MOSFET analog circuit, which is proposed to replace the traditional bootstrap switches. The total sampling time spans 16 clock periods, with a corresponding sampling frequency of 3.125 MHz. Furthermore, the integration of a synchronous dynamic SAR-logic module within the ADC substantially minimizes power consumption to 3.28 mW. The ENOB, SNR and SFDR of the ADC are 10.52 bits, 65.09 dB and 71.69 dB, respectively, thereby demonstrating excellent performance characteristics that align well with anticipated requirements. All the simulation are processed by Cadence IC.