High-Performance Bayesian Neural Network Inference Accelerator Based on FPGA

Bayesian Neural Networks (BNNs) offer robust uncertainty estimation capabilities through probabilistic modeling, yet their prohibitively high computational complexity and resource consumption limit deployment in edge computing. In this paper, we propose an FPGA-based BNN inference accelerator that optimizes critical modules—including weight generation and Feed-Forward inference. By integrating pipelining techniques with distributed storage strategies, our design achieves a balanced trade-off between computational efficiency and resource utilization. Experimental results on the Xilinx ZYNQ7020 platform demonstrate that, at a 100 MHz clock frequency, the accelerator achieves a single-inference latency of 0.05 seconds, achieving speedups of 254.8× and 6.2× over CPU and GPU platforms, respectively, while offering 28.4× higher energy efficiency than GPUs and maintaining a recognition accuracy of 98.4%.

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Publication Details

Journal
IEEE transactions on circuits and systems for artificial intelligence.
Published
2025-01-01
DOI
https://doi.org/10.1109/tcasai.2025.3614509
Primary Topic
Fault Detection and Control Systems
Type
article
Field-Weighted Citation Impact
0.00
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article

High-Performance Bayesian Neural Network Inference Accelerator Based on FPGA

Xueyan Wang, Jianlei Yang, Bingyue Zhang, Weisheng S. Zhao et al.
IEEE transactions on circuits and systems for artificial intelligence.
Fault Detection and Control Systems
article

High-Performance Bayesian Neural Network Inference Accelerator Based on FPGA

Xueyan Wang, Jianlei Yang, Bingyue Zhang, Weisheng S. Zhao, Xiaotao Jia, Z. Wu
article en

Abstract

Bayesian Neural Networks (BNNs) offer robust uncertainty estimation capabilities through probabilistic modeling, yet their prohibitively high computational complexity and resource consumption limit deployment in edge computing. In this paper, we propose an FPGA-based BNN inference accelerator that optimizes critical modules—including weight generation and Feed-Forward inference. By integrating pipelining techniques with distributed storage strategies, our design achieves a balanced trade-off between computational efficiency and resource utilization. Experimental results on the Xilinx ZYNQ7020 platform demonstrate that, at a 100 MHz clock frequency, the accelerator achieves a single-inference latency of 0.05 seconds, achieving speedups of 254.8× and 6.2× over CPU and GPU platforms, respectively, while offering 28.4× higher energy efficiency than GPUs and maintaining a recognition accuracy of 98.4%.

IEEE transactions on circuits and systems for artificial intelligence.
Beijing Advanced Sciences and Innovation Center (CN), Beihang University (CN)
Openalex Percentile: Top 67%
Fault Detection and Control Systems
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