High-Performance Bayesian Neural Network Inference Accelerator Based on FPGA
Bayesian Neural Networks (BNNs) offer robust uncertainty estimation capabilities through probabilistic modeling, yet their prohibitively high computational complexity and resource consumption limit deployment in edge computing. In this paper, we propose an FPGA-based BNN inference accelerator that optimizes critical modules—including weight generation and Feed-Forward inference. By integrating pipelining techniques with distributed storage strategies, our design achieves a balanced trade-off between computational efficiency and resource utilization. Experimental results on the Xilinx ZYNQ7020 platform demonstrate that, at a 100 MHz clock frequency, the accelerator achieves a single-inference latency of 0.05 seconds, achieving speedups of 254.8× and 6.2× over CPU and GPU platforms, respectively, while offering 28.4× higher energy efficiency than GPUs and maintaining a recognition accuracy of 98.4%.
Authors
- Xueyan Wang (ORCID: https://orcid.org/0009-0009-0808-8995)
- Jianlei Yang (ORCID: https://orcid.org/0000-0001-8424-7040)
- Bingyue Zhang
- Weisheng S. Zhao (ORCID: https://orcid.org/0000-0001-8088-0404)
- Xiaotao Jia (ORCID: https://orcid.org/0000-0003-2207-6092)
- Z. Wu
Institutions
- Beijing Advanced Sciences and Innovation Center (CN)
- Beihang University (CN)
Publication Details
- Journal
- IEEE transactions on circuits and systems for artificial intelligence.
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1109/tcasai.2025.3614509
- Primary Topic
- Fault Detection and Control Systems
- Type
- article
- Field-Weighted Citation Impact
- 0.00