Calibrating DRAMPower Model for HPC: A Runtime Perspective from Real-Time Measurements

Main memory's rising energy consumption has emerged as a critical challenge in modern computing architectures, particularly in large-scale systems, driven by frequent access patterns, growing data volumes, and insufficient power management strategies. Accurate modeling of DRAM power consumption is essential to address this challenge and optimize energy efficiency. However, existing modeling tools often rely on vendor-provided datasheet values that are obtained under worst-case or idealized conditions. As a result, they fail to capture important system-level factors such as temperature variations, chip aging, and workload-induced variability, which leads to significant discrepancies between estimated and actual power consumption observed in real deployments. In this work, we propose a runtime calibration methodology for the DRAMPower model using energy measurements collected from real-system experiments. By applying custom memory benchmarks on an HPC cluster and leveraging fine-grained power monitoring infrastructure, we refine key current parameters (IDD values) in the model. Our calibration reduces the average energy estimation error to less than 5%, substantially improving modeling accuracy and making DRAMPower a more reliable tool for power-aware system design and optimization on the target server platform.

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Publication Details

Journal
IEEE Computer Architecture Letters
Published
2025-01-01
DOI
https://doi.org/10.1109/lca.2025.3615711
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
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article

Calibrating DRAMPower Model for HPC: A Runtime Perspective from Real-Time Measurements

Thomas Ilsche, Francky Catthoor, Timon Evenblij, Saeideh Alinezhad Chamazcoti et al.
IEEE Computer Architecture Letters
Parallel Computing and Optimization Techniques
article

Calibrating DRAMPower Model for HPC: A Runtime Perspective from Real-Time Measurements

Thomas Ilsche, Francky Catthoor, Timon Evenblij, Saeideh Alinezhad Chamazcoti, Mohit Gupta, Xinyu Shi, Dina Abdelbaky
article en

Abstract

Main memory's rising energy consumption has emerged as a critical challenge in modern computing architectures, particularly in large-scale systems, driven by frequent access patterns, growing data volumes, and insufficient power management strategies. Accurate modeling of DRAM power consumption is essential to address this challenge and optimize energy efficiency. However, existing modeling tools often rely on vendor-provided datasheet values that are obtained under worst-case or idealized conditions. As a result, they fail to capture important system-level factors such as temperature variations, chip aging, and workload-induced variability, which leads to significant discrepancies between estimated and actual power consumption observed in real deployments. In this work, we propose a runtime calibration methodology for the DRAMPower model using energy measurements collected from real-system experiments. By applying custom memory benchmarks on an HPC cluster and leveraging fine-grained power monitoring infrastructure, we refine key current parameters (IDD values) in the model. Our calibration reduces the average energy estimation error to less than 5%, substantially improving modeling accuracy and making DRAMPower a more reliable tool for power-aware system design and optimization on the target server platform.

IEEE Computer Architecture Letters
IMEC (BE), Technische Universität Dresden (DE)
Openalex Percentile: Top 71%
Parallel Computing and Optimization Techniques
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