A Low-Jitter Fractional- <i>N</i> Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration

This work presents a 10.0–11.5-GHz fractional-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> digital phase-locked loop (DPLL) using the quantization-error-compensating bang–bang phase detector (QEC-BBPD) that can minimize both the static delay (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {S}}$</tex-math> </inline-formula>) and the dynamic delay (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {D}}$</tex-math> </inline-formula>) required for removing the delta-sigma modulator’s (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $</tex-math> </inline-formula>M) quantization-error (Q-error). Since the proposed QEC-BBPD reduces additional thermal noise during the Q-error-compensation process, it allows the DPLL to achieve low in-band phase noise (PN) and low rms jitter. Along with the QEC-BBPD, this work also presents the orthogonal-polynomial-based least-mean-square multivariable calibration (OP-LMS MVC) to accelerate the calibration speed for the removal of the nonlinearities (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NL</i>s) of the QEC-BBPD with minimal hardware overhead. The fractional-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> DPLL in this work, fabricated in a 40-nm CMOS process, occupied 0.12 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon and consumed 14.4mW of power. The rms jitter and worst fractional spur were 64 fs and −62.8 dBc, respectively, at a fractional-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> frequency near 10.9 GHz. It achieved the lowest in-band PN and the best normalized jitter-power figure-of-merit for the multiplication factor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> (FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathrm {jitter,}N}$</tex-math> </inline-formula>), i.e., −272.2 dB, among the state-of-the-art fractional-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> phase-locked loops (PLLs).