An 8.5 MHz 42 ppm/∘ <sup>C</sup> Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation

This paper presents an RC oscillator featuring a mixed-signal compensation loop that simultaneously mitigates comparator offset, loop delay, switch on-resistance, and temperature dependency. The oscillator employs an auxiliary comparator, a charge pump and a differential difference amplifier (DDA)-based main comparator to suppress ramping voltage overshoots caused by device and loop imperfections. Moreover, the auxiliary comparator employs chopper and digital demodulation techniques to suppress its own offset, further enhancing the accuracy of the calibration loop. By generating both ramping and reference voltages, the proportional-to-absolute-temperature (PTAT) core ensures that the temperature coefficient (TC) of the oscillation frequency primarily depends on passive RC components. Fabricated in a 0.18 μm BCD process, the design achieves an average frequency TC of 42 ppm/∘C from -20 ∘C to 125 ∘C across 10 samples. Benefiting from the proposed architecture, the oscillator operates at 8.45 MHz with a fast startup calibration time of 50 μs.

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Publication Details

Journal
IEEE Solid-State Circuits Letters
Published
2025-01-01
DOI
https://doi.org/10.1109/lssc.2025.3615833
Primary Topic
Advancements in PLL and VCO Technologies
Type
article
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article

An 8.5 MHz 42 ppm/∘ C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation

Yongjia Li, Zhongyuan Fang, Dejin Wang, Jin Wu et al.
IEEE Solid-State Circuits Letters
Advancements in PLL and VCO Technologies
article

An 8.5 MHz 42 ppm/∘ C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation

Yongjia Li, Zhongyuan Fang, Dejin Wang, Jin Wu, Long Zhang, Xiaofeng Sun, Yifan Cao, Weifeng Sun, Jianlin Xia, Cheng Feng, Encheng Zhu
article en

Abstract

This paper presents an RC oscillator featuring a mixed-signal compensation loop that simultaneously mitigates comparator offset, loop delay, switch on-resistance, and temperature dependency. The oscillator employs an auxiliary comparator, a charge pump and a differential difference amplifier (DDA)-based main comparator to suppress ramping voltage overshoots caused by device and loop imperfections. Moreover, the auxiliary comparator employs chopper and digital demodulation techniques to suppress its own offset, further enhancing the accuracy of the calibration loop. By generating both ramping and reference voltages, the proportional-to-absolute-temperature (PTAT) core ensures that the temperature coefficient (TC) of the oscillation frequency primarily depends on passive RC components. Fabricated in a 0.18 μm BCD process, the design achieves an average frequency TC of 42 ppm/∘C from -20 ∘C to 125 ∘C across 10 samples. Benefiting from the proposed architecture, the oscillator operates at 8.45 MHz with a fast startup calibration time of 50 μs.

IEEE Solid-State Circuits Letters
China Resources (China) (CN), Hua Hong Semiconductor (China) (CN), Southeast University (CN)
Openalex Percentile: Top 74%
Advancements in PLL and VCO Technologies
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