Prebond Test of TSV Based on Voltage Skew Amplification

In the manufacturing process of integrated chips, numerous defects may occur in through-silicon vias (TSVs), which can affect the integrity of signals passing through the TSVs. Therefore, it is crucial to detect these defects in the early stages of production. Existing testing methods suffer from issues such as large testing areas and time overhead, as well as low testing accuracy. In this paper, an nMOS is selected as the gating device to reduce the area overhead of shared testing. A voltage comparator is employed to amplify the voltage difference between the TSV under test and a reference capacitor, enabling the detection of resistive open defects with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">open</sub> ≥ 39 Ω, leakage defects with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">leak</sub> ≤ 5 MΩ. Compared with other methods, this approach offers the advantages of high detection accuracy for resistive open defects and minimal testing area and time overhead.