Scalable Yield Analysis of SRAM and Analog Circuits Using Multi-Kernel Sparse Representation

With the advancement of technology nodes and the increasingly stringent requirements for stability, general yield analysis of customized circuits in the early stages of design has become a key bottleneck in manufacturing. In this article, we propose a multi-kernel sparse representation-based classification (MKSRC) method to enhance the efficiency and scalability of failure probability estimation by classifying tail samples. It employs class-balanced sampling to address data imbalance issues and utilizes multi-kernel features with adaptive kernel weights to enhance the accuracy and robustness of the classifier. Experimental results on 32-bit SRAM columns and analog circuits demonstrate that the proposed MKSRC method achieves higher classification accuracy and efficiency compared to other state-of-the-art methods, particularly in scenarios with limited training data. Compared to SOTA yield estimation methods, the MKSRC method achieves an average 2.57–3.29× improvement in both accuracy and efficiency, highlighting its ability to provide efficient and scalable yield analysis solutions for both SRAM and analog circuits.