Design of 12‐T SRAM Circuit for Horizontal and Vertical Content‐Addressable Memory

ABSTRACT Conventional static random‐access memory (SRAM) architectures have only row‐addressing modes, being prone to have large dynamic power consumptions during cross‐row/column data addressing and per‐bit logic operations. This paper proposes a 12‐transistor (12‐T) SRAM circuit that enables multi‐bit in‐memory logic operations, including AND, NOR, A AND B′, and A′ AND B, while supporting configurable binary/ternary content‐addressable memory (BCAM/TCAM) functions for both row and column directions. By integrating dual‐directional row/column readout modes, the design addresses signal crosstalk issues, reducing operating power consumption with enhanced system stability. Compared with conventional SRAM, the proposed circuit achieves 554 MHz (row) and 556 MHz (column) operating frequency at operating voltage of 1.2 V, leading to a 50.6% frequency improvement. Even at a reduced supply voltage of 0.8 V, the design maintains 203 MHz operation, demonstrating robust low‐voltage compatibility. Furthermore, in the logic mode, the circuit attains an energy efficiency of 1.96 fJ/search/bit, significantly outperforming prior works. As the proposed SRAM seamlessly supports transitions between SRAM, BCAM/TCAM, and logic modes, it is versatile for high‐speed search, parallel data matching, and energy‐efficient in‐memory computing applications.