A hybrid SRAM array architecture using single port and dual port 7T SRAM cells for low power applications

Abstract The increasing demand for longer battery life of portable devices has fueled research towards power reduction for memory circuits. Conventionally, a memory array is designed by replicating a single bit cell to form m × n array. Thus, the conventional mechanism to lower memory power is by optimizing the bit cell power; whereas, power consumption for memory may be lowered by re-designing the memory array. Thus, in this paper a new hybrid array configuration is proposed to lower power consumption. The proposed memory array is designed using two different 7T cell configurations - single port and dual port. The purpose of using two cell configurations in place of a single cell is that, not all bits in a word (row) are of the same importance. The performance of the proposed hybrid array is analyzed for 8 kB memory, with 512 rows and 16 columns. Least static power value is obtained for partition of four 7TD cell—twelve 7TS cells at 0.271 μW. While, the highest static-power is obtained for array designed using dual port cells at 0.367 μW. The least dynamic-power is obtained for four 7TD—twelve 7TS cell array at 21.58 μW. While, the highest dynamic-power is obtained for conventional dual-port based array at 28.9 μW. But, the best results are obtained when the array partition is six dual port and ten single port cells. The static and dynamic power values obtained for this design configuration are 0.29 μW and 2 3μW respectively.