A Review of Performance and Reliability Issues in D Flip‐Flops for Future Artificial Intelligence and Internet of Things Applications

In this paper, various D flip‐flops (FFs) (DFFs) are studied and analyzed based on the performance and reliability effects of different architectures, technology, area, power, delay, and several other key performance parameters of DFFs. Based on these parameters, a few selected DFFs such as C2SFF, conditional‐bridging FF (CBFF)‐S, self‐shut‐off pulsed latch (SSPL), retentive true signal phased clock (R‐TSPC), mTGFF, mC2MOS, FS‐TSPC‐DET‐FF, and P‐FF, are briefly reviewed for different architectures and technologies, with the trade‐off between the various performance parameters discussed in this paper. Comparative analysis is done for the selected DFFs on technology, supply voltage, set‐up time, delay, power consumption, and area. Reliability effects on DFFs and aging effect on FFs are reviewed for timing yield‐aware lifetime reliability (TYR) based on the process variations (PVs) and bias temperature instability (BTI). A brief review on applications of DFFs in internet of thing (IoT) devices and artificial intelligence (AI), such as frequency divider, dual‐modulus prescaler, time‐to‐digital converter (TDC), shifter, and synchronizer, is also presented.