Performance-Complexity Tradeoff for ISAC Transceiver Design: A Deep Unfolding Method
Integrated sensing and communication (ISAC) can boost the spectrum efficiency and facilitate the diverse emerging applications via sharing the same spectrum and hardware between communication and sensing. However, it may suffer from high complexity. In this paper, we develop a low-complexity deep unfolding learning aided transceiver design for ISAC. Particularly, the weighted sum of multi-user interference power and the reciprocal of sensing signal-to-interference-plus-noise ratio is minimized subject to the constraints of constant modulus signal and waveform similarity by transceiver design. An alternating direction method of multipliers (ADMM)-based iterative algorithm is first developed to solve this non-convex optimization problem. To reduce the complexity, we propose a deep unfolding neural network (NN), which can unfold the underlying ADMMbased iterative algorithm to a lightweight NN with some learnable parameters and circumvent the bisection method using the projected gradient descent. Simulation results demonstrate the effectiveness of our proposed deep unfolding NN.
Authors
- Derrick Wing Kwan Ng (ORCID: https://orcid.org/0000-0001-6400-712X)
- Yongxu Zhu (ORCID: https://orcid.org/0000-0002-5413-1968)
- Shi Jin (ORCID: https://orcid.org/0000-0003-0271-6021)
- Naofal Al‐Dhahir (ORCID: https://orcid.org/0000-0001-9894-8382)
- Nan Zhao (ORCID: https://orcid.org/0000-0002-6497-7799)
- Xianbin Wang (ORCID: https://orcid.org/0000-0003-4890-0748)
- Jifa Zhang (ORCID: https://orcid.org/0000-0002-0488-6940)
Institutions
- Western University (CA)
- The University of Texas at Dallas (US)
- Dalian University of Technology (CN)
- UNSW Sydney (AU)
- Southeast University (BD)
- Southeast University (CN)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.1109/icc52391.2025.11161873
- Citations
- 1
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 2.27