Revisiting Logic Compaction Aspects of Minority-Majority-Inverter Graph (mMIG) Circuits

In the post-CMOS era, emerging data structures for logic synthesis and technology mapping have gained importance for efficient design automation. Majority Inverter Graph (MIG) is a homogeneous structure of majority and inverter nodes that has become a prominent data structure for compact logic synthesis and optimization. This paper demonstrates that minority majority inverter graph (mMIG) based logic synthesis leads to reduced inverter operations. We propose revised transformation rules for mMIG, such as associativity, distributivity, swapping reconvergence, and swapping non-reconvergence. With mMIG-based synthesis of Addition-Rotation-XOR (ARX) S-boxes, namely MARX-2 and SPECKEY and 8-bit, 16-bit adders, we show the reduction in critical path delay compared to MIG and And-Or-Inverter Graph (AOIG) logic synthesis. We report that a circuit implemented in mMIG can be driven with a maximum clock frequency of 880.35 MHz in comparison to AOIG synthesized circuit on the same FPGA device.