Interconnect Parasitic-Aware Power MOSFETs Layout in DC-DC Converter for Efficiency Optimisation and Uniform Current Distribution

In on-chip DC-DC converters, the parasitic interconnect resistance due to metal routing in the power MOSFETs may be significant if not managed properly. This issue degrades the power conversion efficiency and leads to a non-uniform current distribution in the power MOSFETs creating multiple hotspots. This paper introduces an interconnect parasitic-aware power MOSFETs layout design for optimising efficiency and achieving a uniform current distribution. It also improves the design reliability. A current-mode DC-DC buck converter switching at 20 MHz is implemented in 0.18 μm CMOS process targeting to deliver a maximum current of 1 A with V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</inf> = 2.7-3.3 V, V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</inf> = 1.2 V as a case study. In the full-chip layout, the interconnect resistance and the current density profile of the power MOSFETs are estimated accurately. The proposed method helps to identify the epicentre of a high-parasitic region in an unoptimized layout. This feature is powerful for minimising the interconnect parasitic in the power MOSFETs layout with less design effort and iteration. The post-layout simulation result confirms that in an optimised power MOSFETs layout, the power efficiency degrades by only ~ 2.8% at full load condition due to interconnect resistance and achieves a uniform current distribution.