Nanoscale Computing: Assessment of Hardware Platforms for Machine Learning by Transformer Models
The performance in terms of execution time of Transformer-based models when run on edge-computing platforms is hard to predict, because it depends on many factors such as the nanoscale technology used for implementation or model architecture. Another dimension of interest when evaluating the execution time is the size of the model, as in many cases, several versions of the model with different sizes can be used. The smaller size versions reduce significantly the number of parameters and thus of the nanoscale memory and arithmetic operations needed to run the model, however this does not necessarily map to similar reductions in execution times. This paper studies the relation between model size and execution time by evaluating three different Transformer-based models: Bidirectional Encoder Representations from Transformer (BERT), Transfer Text-to-Text Transformer (T5) and Contrastive Language–Image Pre-training model (CLIP), and their corresponding reduced versions when run on three different nanoscale hardware platforms.
Authors
- Fabrizio Lombardi (ORCID: https://orcid.org/0000-0003-3152-3245)
- Weimin Zeng (ORCID: https://orcid.org/0000-0002-7155-6386)
- Yingtao Zhang (ORCID: https://orcid.org/0000-0002-8587-9645)
- Pedro Reviriego (ORCID: https://orcid.org/0000-0003-2540-5234)
- Zhen Gao (ORCID: https://orcid.org/0000-0001-9887-1418)
- Shuang Liu (ORCID: https://orcid.org/0000-0001-8766-7235)
- Shanshan Liu (ORCID: https://orcid.org/0000-0001-6226-2880)
Institutions
- Northeastern University (US)
- University of Electronic Science and Technology of China (CN)
- Tianjin University (CN)
- Universidad Politécnica de Madrid (ES)
Publication Details
- Journal
- IEEE Nanotechnology Magazine
- Published
- 2025-09-26
- DOI
- https://doi.org/10.1109/mnano.2025.3607072
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00