Performance Comparison of Booth-Wallace and Vedic Multiplier Design

Multiplication is an important operation in digital systems, and is critical in fields like microprocessor design, communication systems, application-specific integration circuit (ASIC). Since speed is frequently important, the selection of a multiplication algorithm may have a substantial impact on the performance of the system as a whole. The comparison is done between Booth-Wallace Multiplier and Vedic Multiplier in terms of delay, area and power. Booth-Wallace’s algorithm employs modified Booth encoding so as to minimize the quantity of partial products, thus allowing computation to be faster. On the other hand, The Vedic Multiplier is an efficient multiplier inspired by the Indian ancient mathematical principles and it based on parallel methods of multiplication. In order to compare performance of the two architectures, both multipliers were coded in Verilog HDL and operated under Intel Quartus Prime and ModelSim. Different input conditions were applied to address real world situations and timing study was carried out. Results indicated that the Booth-Wallace Multiplier presented faster delay on average17.863 ns compared with the Vedic 19.667 ns. The difference isn’t large, but it does ostensibly imply some superiority depending on the application. As an outcome, this comparison provides useful know-how for engineers and researchers who are making a decision on selecting suitable multiplications for digital design, especially when the trade-off between performance and hardware constraint is considered.