Recent Progress in Sub‐10 Nm Nanofabrication for Scaling Down 2D Transistors

Abstract 2D field‐effect transistors (2D‐FETs) leverage atomically thin, dangling‐bond‐free channels to overcome short‐channel effects and surface defects in sub‐10 nm nodes. However, conventional lithography hardly meets the requirement of sub‐10 nm nanofabrication because of resolution limits, making the fabrication of 2D‐FETs with sub‐10 nm channel lengths still a significant challenge. Here, strategies of realizing 2D‐FETs are reviewed with sub‐10 nm channels: i) Ultraprecise nanolithography, including electron‐beam lithography, cold development, and block copolymers (BCP)‐based directed self‐assembly (DSA); ii) Nanogap formation, leveraging stress‐induced cracking, grain‐boundary widening, electromigration, carbon‐nanotube masking, and shadow evaporation; iii) Vertical‐channel architectures, where channel length is defined by dielectric thickness in metal–insulator–metal stacks or barristor structures; iv) Self‐aligned isolation, employing ultrathin film oxidation, adhesion lithography, and heterostructure undercut processes to precisely define source‐drain separations. Key performance metrics are compiled and compared—contact resistance, on‐state current, off‐state leakage, DIBL, and subthreshold swing—across representative devices, illustrating the robust scaling immunity of 2D materials. Finally, emerging “lab‐to‐fab” approaches are discussed, such as edge lithography, mechanical cracking, and post‐pattern modification, pointing toward scalable, low‐cost manufacturing of wafer‐scale sub‐10 nm 2D‐FETs. This outlook provides practical guidelines for future integrated circuit implementations based on 2D semiconductors.