Mitigating IEMI Induced Faults in PLL-Based Cryptographic Modules Through Narrow Loop Bandwidth

A threat has been reported in which an intentional electromagnetic interference (IEMI) generates a glitch in the input clock of a phase-locked loop (PLL) circuits, thereby causing a temporary fault in a cryptographic module clocked by the PLL and extracting secret key using the fault outputs. This threat occurs faults based on a timing violation by increasing PLL output frequency to the extent that it exceeds the maximum operation frequency of the cryptographic module by causing a large difference in the phase comparison operation of clock signals by the PLL. To counter this threat, this paper proposes a countermeasure to reduce the fault occurrence by narrowing the loop bandwidth, which determines the frequency response characteristics of PLLs.