A Wideband Static CMOS Divide-by-2 Frequency Divider for Low-Power RF Applications

This paper introduces a novel Static CMOS-based divide-by-2 frequency divider with a switched capacitor array, targeting wideband, low-power RF systems in TSMC 0.18 µm process. It operates from 200 MHz to 11 GHz, consumes under 3 mW, and occupies significantly less than 32,256 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, outperforming CML designs. The design uses a Static CMOS D flip-flop as a T flip-flop with a 0.5-4 pF switched capacitor for frequency tuning, minimizing complexity. Simulations show 2.994 mW at 11 GHz, 25 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area (0.5 pF load, W/L=2 µm/0.18 µm), 1750 mV sensitivity, and -114 dBc/Hz phase noise at 1 MHz offset (4 pF). This surpasses CML’s 3.58 mW and 32,256 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, ideal for 5G, IoT, and satellites, reducing costs. Contributions include innovative architecture and tuning mechanism, validated experimentally. Future work: input buffering for sensitivity, advanced processes, PLL integration. This advances scalable RF dividers for next-generation communications.