Research on Reconfigurable-Granularity MAC Computing Unit for Transformer Models

Transformer models have demonstrated significant success across various domains but face challenges in computational and efficiency due to dense self-attention operations. This paper proposes a reconfigurable-granularity multiply-accumulate (MAC) computing unit, PE, designed to optimize Transformer performance by dynamically adapting computational precision and parallelism based on input sparsity. The proposed architecture integrates zero-detection modules, granularity selectors, and reconfigurable MAC arrays to skip redundant operations and maximize hardware efficiency. It supports fine-grained quantization, enabling bit-level resource adaptation. Experimental analysis and architectural discussion confirm that the proposed unit significantly lowers computational complexity while preserving model accuracy. This work provides a practical hardware-friendly solution for accelerating sparse Transformer workloads and opens avenues for future research in mixed sparsity and quantized training-aware optimization. This work primarily presents a conceptual design of a reconfigurable-granularity MAC unit. However, detailed experimental validation and rigorous performance benchmarking remain outside the scope of this study and are intended as directions for future research.