A 26.7 TOPS/W Multiplier-Less Digital In-Memory Computing Macro with low-cost Multi-Layer Inference in 28nm FDSOI for edge AI

In this paper, a low-power multiplier-less artificial neural network implementation is proposed. Reduced area and power consumption are achieved through the combination of a multiplier-less neuron unit made possible by the use of Powers-of-two (POT) quantization of the network weights, the use of a digital in-memory computing (DIMC) architecture of the neuron, and the implementation of a multi-layer network as a single iterative layer scheme. A 32x32x32x32 (4 layers of 32 neurons) feedforward fully connected network (FNN) has been designed in 28nm FDSOI CMOS. The post-layout simulations show up to 26.7 8-b TOPS/W performance for a 1-layer inference (23.4 8-b TOPS/W for a 4-layer inference) as well as up to 2.1 8-b TOPS/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> performance.