A Minimal Hardware Implementation of a Neural Integrator with Graded Persistent Activity

Cognitive functions, such as working memory and decision making require neurons to maintain an excited state over time. Basic motor functions, such as eye fixation or keeping the position of a limb fixations may require modifying the firing rate of the commanding neurons, and then keeping it stable. These functions are implemented by Neural Integrator (NI) networks and their ability to modify and maintain over time a firing state, is called Graded Persistent Activity (GPA). Although the bio-molecular mechanisms of NI and GPA are unclear, extensive theoretical efforts are dedicated to modeling them. A key ingredient of the neural networks that are investigated is recurrent connectivity. In order to achieve the required features of tunability and stability, the proposed networks are either complex or require fine tuning. In the present work, we introduce a simple model that shows stable GPA and NI behavior, which consists of a single spiking neuron with a recurrent self-excitatory synapse. The synaptic conductance is modulated by integration of external pulses (excitatory and inhibitory), while the stability is assured by a self-consistent firing state. Our model is implemented in analog electronic hardware recently introduced, where the key component is a memristor based on a conventional thyristor device. We describe the behavior of the model in terms of line attractor dynamics that rationalizes the stability and tunability of the sustained activity, which we measured in a circuit. This model may be a basis for a general hardware solution for artificial intelligence cognitive devices.