A GNRFET-based Approach to Design Ternary Logic Arithmetic Circuits

To drive the need for higher density, faster processing and improved energy efficiency beyond the limitations of binary logic, researchers are exploring ternary logic (using states 0, 1, and 2, respectively). This work presents ternary multiplier and comparator circuits implemented using graphene nanoribbon transistors (GNRFETs) that leveraging superior electrical properties. The circuits are deigned from basic and universal gates along with decoder circuits that are simulated using HSPICE at 0.9V of supply. Compared to existing carbon nanotube FET (CNTFET) based ternary multiplier, comparator and subtractor circuits, the proposed GNRFET multiplier, comparator and subtractor designs show significant performance improvements up to 29.50% reduction in power consumption, 41.29% decrease in delay, and a 58.48% improvement in PDP, respectively.