FPGA-Driven Low Power ECG Analyser with Robust Noise Handling

The increasing necessity for wearable medical devices to keep pace with expanding healthcare demands is driving the requirement for effective processing of biomedical signals. This article introduces an FPGA-based system upgraded for ECG heartbeat detection aimed at solving problems of power consumption, noise suppression, and space constraints. Hybrid Carry Select Adders (CSAs) are utilized to greatly boost computationally velocity, lower the critical path delays, and economize on the hardware resources used. The design has been effectively deployed on the Zybo Z7 FPGA board with Vivado and exhibited good hardware functionality. Experimental findings confirm the system's high accuracy in processing ECG signals, minimal hardware footprint, and enhanced power and timing efficiency. The improved design provides a basis for real-time applications in wearable and portable medical devices.