Hardware-Aware Neural Architecture Search for Memory constrained Embedded Neural Networks Accelerators

In this paper we propose a Hardware-Aware Neural Architecture Search method focused on memory constrained neural networks accelerators. Our solution is based on the observation that minimizing data transfers to and from the accelerator while maximizing the number of operations can lead to efficient network design. We introduce an optimized search space integrated into a NAS algorithm providing networks that improve the latency while minimizing the energy consumption. Those networks also achieve a better accuracy when compared to manually designed mobile architectures. Our experimental results, performed on Imagenet, show that the accuracy can be improved by 1.3% for a specific range of latencies compared to different versions of MobileNetV2 rescaled by hand.