Design and Implementation of Multi-channel Synchronous Acquisition Based on JESD204B Protocol

This paper designs a multi-channel synchronous acquisition board with multi-chip ADCs. By utilizing the deterministic delay characteristics of the JESD204B protocol and designing control logic for SYSREF signals in a reasonable manner, data synchronizationbetween channels can be achieved to ensure that the phase of the signals from each channel is consistent. The test logic board is designed based on Xilinx K7 series FPGA and four GM4680-1000 chips. The test results show that the design meets the application requirements. This method can provide a technical foundation for future synchronous acquisition applications of digital array radar.