Investigation and Design of a Ka-band GaN MMIC Power Amplifier with Miniaturized Chip Area

This paper presents a compact two-stage power amplifier optimized for limited chip area in the Ka-band, based on a 120nm GaN-on-SiC process. It addresses the limitations of traditional harmonic control techniques for miniaturized designs by comparing the performance of compact bandpass matching networks and harmonic control networks. The analysis reveals that harmonic control technology imposes significant restrictions on the improvement of power added efficiency and gain under size constraints. To overcome these challenges, the design adopts a T-network output matching network strategy and verifies the electromagnetic coupling effects between different stages by optimizing the circuit layout and dimensions. This approach enables circuit miniaturization while maintaining stability. Circuit results demonstrate that the power amplifier achieves Gain> 16 dB and drain efficiency (DE) >28% within the frequency range of 27.5 to 31 GHz, with a core chip area of only 1.5 × 1.8 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.