Computation-Efficient Hardware Accelerator for Unstructured-Pruned Spiking Convolutional Neural Networks

Spiking neural networks, which closely mimic biological neurons, are known for their excellence in event-driven tasks. However, the additional temporal dimension increases forward propagation time, latency, and design complexity. To address these challenges, this paper proposes an efficient weight encoding and dataflow for spiking convolutional neural networks (SCNN). This design accelerates inference, reduces memory footprint, and supports reconfigurable kernel sizes and strides. It can reduce SCNN memory footprint by over 40% with small time steps. The hardware accelerator achieves a computational efficiency of 2.93 KFPS/W on the MNIST dataset and 0.55 KFPS/W on the CIFAR-10 dataset, demonstrating a significant advantage over other state-of-the-art designs and highlighting the potential of our method in achieving higher computational efficiency for SCNNs.