Layout Parasitics Extraction of DC–DC Converters for Virtual Reference Designs in InfineonSpice

Power electronics electrical performance depends largely on the layout design and its parasitic effects such as stray inductances. This paper presents a novel holistic approach to extract printed circuit board (PCB) layout parasitics and include them into the circuit simulator InfineonSpice to predict the electrical transient behavior of a 48 V–12 V dc–dc converter real reference design. Dedicated stray inductances of the layout are extracted by different industry-standard electromagnetics (EM) simulators and compared with vector network analyzer measurements. The entire PCB layout parasitics are extracted and imported into the circuit simulator InfineonSpice. The resulting virtual reference design (VRD) is run to steady state and exhibits a close correlation to the real reference design, which is validated by time-domain measurements with fiber optic oscilloscope probes.