Design and Implementation of Low-Power Binary CNN Architectures on VLSI for UART-Enabled IoT Applications

This paper presents the design and implementation of a high-performance binary-weighted convolutional artificial neural network tailored for UART-based applications. The proposed architecture leverages VLSI implementation to achieve notable improvements in computational efficiency, power consumption, and hardware resource utilization. Specifically optimized for binary-weighted operations, the design simplifies convolutional computations while maintaining high accuracy. The framework incorporates optimized binary multipliers, compressors, and approximate adders to enhance power efficiency and ensure high throughput. A comprehensive analysis and comparison across 8-bit, 16-bit, and 32-bit configurations were conducted, demonstrating that the 8-bit implementation offers distinct advantages in terms of power efficiency, area optimization, and timing performance. Experimental evaluations and simulation results validate the effectiveness of the proposed system. Furthermore, the architecture was verified through simulation and synthesis on FPGA platforms, illustrating its capability to efficiently process visual data. Prospective integration with embedded vision systems and IoT applications is also discussed as a future extension of this work.