Reconfigurable Dataflow and Tile Shape Optimization in SystemC-Based NoC of 1D PE Array Simulators integrated with TVM

Data reuse and hardware architecture are the keys to design a high performance accelerator. Dataflow, composed of loop tiling, loop ordering, and parallelization, directly impacts the data reuse of DNN accelerators. Traditional accelerators, such as 2D-mesh Processing Element (PE) arrays, systolic arrays, or 1D PE arrays, have some issues. The 2D-mesh PE array or systolic array can handle large-scale models but lack flexible data configuration. The 1D PE array architecture offers flexibility but faces scalability issues, limiting its application in large models.We propose a new architecture called Network-on-Chip (NoC) 1D PE array, that replaces the PE in the 2D-mesh with 1D PE array to overcome the scalability and flexibility problems. We implement a NoC-based 1D PE array simulator using SystemC integrated with TVM. This simulator supports flexible dataflow and tile size configurations, enabling efficient performance estimation for DNN models. The NoC architecture allows various configurations, providing a nearly cycle-accurate performance model. TVM integration automates performance estimation, optimizing tiling and dataflow strategies for each layer, supporting various DNN frameworks. We evaluate the performance of different dataflows and tile sizes on VGG16 and it shows a 1.84x speed up compared to state-of-the-art under the same number of PEs.