Multiple PDN Design Optimization Using Deep Reinforcement Learning for Low PSIJ in PCIe Gen6.0 Interfaces

This paper introduces a multiple PDN optimization method for merging power rails within SSDs, addressing both interactions between merged rails and noise coupling from printed circuit board (PCB) or package (PKG) power delivery network (PDN) layouts. The method aims to meet target power supply-noise induced jitter (PSIJ) requirements while minimizing the use of components such as decoupling capacitors (decaps) and ferrite beads by optimizing their PCB placements. To effectively optimize complex systems, we enhance the Proximal Policy Optimization (PPO) algorithm by applying an adaptive parameter noise (APN) techniques to the actor/critic network. We validate our approach by comparing self and coupling peak-to-peak jitter, as well as component counts, against a baseline PDN designed by engineers and a standard PPO without an APN technique, demonstrating superior performance.