Design and FPGA Implementation of Secure Parking System

In the realm of Metropolitan traffic management, the design and implementation of a secure vehicle parking system using Verilog HDL stands as a guide of innovation. This research paper explores the complexities of creating a robust system that not only assigns parking spaces to vehicles but also protects the process with a password-based entry and exit. Utilizing the precision and efficiency of Verilog HDL, the system is organized to allocate parking slots upon vehicle arrival, which are then locked and unlocked using a distinct password. This provides a high level of security and prevents unauthorized access. In addition to this, the system also calculates the parking duration for each vehicle, a quality that is important for fair billing and optimal space management. The design of this system using Verilog HDL and implementation on ARTIX-7 FPGA Board exhibits a notable advancement in parking solutions, offering a scalable, protective, and efficient approach to manage vehicle parking in congested metropolitan environments.