Low-Complex Architecture for Parameter Extraction From EEG-Based Phase Lag Index Function Connectivity Matrix

Design a low-complex architecture for extraction of graph theoretic parameters from electroencephalography (EEG) based PLI functional connectivity matrix quantitative. In this paper, a PLI functional connectivity matrix architecture is optimized, and less computation and less complex graphtheoretic parameters architectures are proposed. The proposed architectures for the PLI matrix and graph-theoretic parameters were developed for a 19 -channel EEG system. The architecture consumes about $72 \%$ of logical resources of FPGA board Artix7 (xc7a200tfbg484-2L) and the latency takes about $\mathbf{6 8} \mu$ s of with 27 MHz operating frequency. The proposed architecture is also synthesized using Synopsys tools employing 90 nm cell libraries of CMOS Application Specific Integrated Circuit (ASIC) technology. It consumes 27 mW power and $25327 \mu \mathrm{~m}^{2}$ of area with 56 MHz operating frequency. The proposed architecture is able to construct a functional connectivity matrix and determine the graph-theoretic parameters from the functional connectivity matrix by consuming less area and power.