Effect of Traps in Si/SiGe NPN Selectors for Cross-Point Memory Array Architecture

A latch-up bipolar junction transistor (BJT) selector device for memory crossbar architecture was fabricated using p<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup>–Si<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{{1}-{x}}$</tex-math> </inline-formula>Ge<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _x </i> as floating base sandwiched between n<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup>-Si layers. The Ge concentration in the SiGe layers has varied between 25% and 40% and the base thickness between 25 and 35nm. The stack was etched with diameter of the device varied from 50 to 150nm. Finally, the devices were encapsulated using different materials. By using end of line (EOL) high-pressure (HP) H<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing, the latch-up voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {on}}\text {)}$</tex-math> </inline-formula> reduced from 2.75 to 2.2V (for 150-nm device diameter) and the nonlinearity (NL = ratio of currents at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {on}} +100$</tex-math> </inline-formula>mV and that at the half of operating voltage) improved from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times 10^{{4}}$</tex-math> </inline-formula>. This behavior was also studied by 1-D technology computer aided design (TCAD) simulation by introducing traps in the device. Traps at the floating base cause loss of hole, resulting in increased latch-up voltage and elevated leakage current. AlO<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _x </i> and SiN<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _x </i> offer superior passivation to deposited SiO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>, enhancing device performance. The device demonstrates excellent performance, achieving a low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {on}}$</tex-math> </inline-formula> of 2.2 V, exceptional endurance exceeding <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{10}}$</tex-math> </inline-formula> cycles (under 0–3 V stress for 100 ns), and a high <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state current density of 14MA/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 3 V. The results demonstrate the viability of the fabricated n-type/p-type/n-type (NPN) device as a high-endurance selector for crossbar memory architectures.