Efficient FPGA Implementation of Hybrid ECG Data Compression for Remote Health Monitoring

The FPGA implementation of a lossless ECG data compression system for minimizing storage requirements and power consumption while preserving signal integrity. The compression method implemented in this work incorporates a combination of Run-Length Coding (RLC) and Golomb-Rice Encoding with an adaptive linear prediction approach to effectively leverage the redundancy inherent in ECG signals. An adaptive predictor is used to forecast future samples of the signal, and prediction error is encoded using variable-length coding to achieve effective compression and low data rate. The architecture is implemented in Verilog HDL and verified on a Xilinx Virtex-5 FPGA. Detailed performance analysis is done in terms of area, delay, and power consumption, indicating the effectiveness of the suggested method for hardware-based real-time and low-power compression of ECG data. We achieved a compression ratio of 2.75 and the architecture implemented consumes power of 87mW at 100MHz operating frequency.