Navigating the Design Space: Analyzing Full Adder Implementations for Power and Delay Optimization

Objective: This study aims to examine seven distinct design methods for creating Full Adder circuits, from simple gate-level designs to more complex transistor-level and mirror adder architectures. The main emphasis is on analyzing and optimizing power usage and propagation delay using Cadence Virtuoso. In this paper Cadence Virtuoso is used to analyze and simulate seven different design methods for Full Adder circuits. These methods include implementations using NAND gates, NOR gates, $2 \times 1$ multiplexers, half-adders, transistors, logic gates, and mirror adders. Formulated logical expressions and circuit diagrams for each method and perform simulations to assess power usage and propagation delay under various input conditions. This paper provides thorough analyses and simulation results for each Full Adder implementation technique. Measurements of power usage and propagation delay are given for each method, providing insights into their efficiency and performance characteristics. The findings are made clear through graphical representations and tabulated data.