A High-Precision Third-Order Sigma–Delta Modulator Circuit Design

To address key challenges in high-precision Sigma–Delta modulator design, such as the trade-off between noise and power consumption and the control of nonlinear distortion, this paper proposes a high-precision third-order Sigma–Delta modulator circuit design. The modulator adopts a fully differential circuit architecture and introduces a time-division multiplexed single-sampling capacitor technique, which reduces capacitor mismatch errors while optimizing the integrator’s noise performance. Combined with the time-division multiplexing strategy, charge injection effects are further suppressed. In the core module design, the integrator employs a folded-cascode amplifier to satisfy the requirements for high precision and high speed; the sampling switch utilizes an improved gate-voltage bootstrap structure, which enhances the linearity of the on-resistance while improving the switching speed, thereby enhancing the modulator’s linearity; the dynamic comparator module achieves low-power quantization through a two-stage latch mechanism. Simulation results based on a 180-nm CMOS process verify that, at a 5[Formula: see text]MHz sampling frequency with a 128 oversampling ratio, the modulator’s total power consumption is 3.53[Formula: see text]mW. The Effective Number Of Bits (ENOB) reaches 14.20 bits, with a Signal-to-Noise Ratio (SNR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of 87.2 and 84.3[Formula: see text]dB, respectively.