Designing of AES-128 Encryption Algorithm Using System Verilog VLSI

This paper details a comprehensive study on the implementation of the Advanced Encryption Standard (AES) using Very Large Scale Integration (VLSI) technology for the purpose of creating efficient hardware-based encryption. AES is widely known for its strength in security, flexibility, and applicability in so many arenas-from data encryption in mobile devices to network communications. The focus of this discussion is the optimization of AES on critical performance metrics of VLSI: power consumption, processing speed, and silicon area efficiency. In this work, we addressed the relevant challenges posed by AES hardware with hardware-efficient pipelining techniques, using 128 bit key, latency has been reduced, and throughput improved; hence, devices with resource constraints are very beneficial for such architectures. Therefore, the findings of the study contribute to pushing forward such secure high-speed solutions in ICs, something much needed on surging demands in IoT as well as in embedded systems.