Back-Biasing Strategy to Mitigate TID-Induced Threshold Voltage Shift in 22nm FDSOI Transistors

In a 22nm FDSOI CMOS technology architecture, it is shown that back-biasing for mitigating total-ionizing-dose (TID) effects accelerates threshold voltage shift (ΔV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub>) by increasing the rate of buried oxide (BOX) trapped charge accumulation. Typical strategies of dynamic back-biasing (DBB) aim to keep ΔV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> near zero by continuously adjusting the back-gate voltages as total dose increases, but this consequently accelerates BOX charge accumulation due to increased electric field strength in the BOX. A novel DBB strategy proposed in this work defers compensatory back-biasing until the threshold voltage approaches its operational limit, which can minimize early charge accumulation and reduce long-term degradation. Experimental results across various device sizes demonstrate that this approach lowers the percentage increase in ΔV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> due to back-biasing for TID mitigation. For example, in an 80/32 nm NMOS device, the deferred DBB strategy reduced pre- and post-annealing ΔV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> increases due to back-biasing to 2% and <1%, compared to 17% and 12% when typical back-biasing is used. This strategy effectively mitigates TID-induced degradation, enhancing device reliability.